Kurs: Entwurf eingebetteter Systeme mit Digitallogik

Beschreibung

VAK 03-ME-712.05
Category: Lecture+Lesson, 4 SWS
Master Course
ECTS: 6, Winter Semester
University of Bremen
Lecturer: PD Dr. Stefan Bosse


This lecture is intended to give an introduction to embedded system design with digital logic and application-specific configurable digital logic hardware using VHDL synthesis.
Hardware synthesis is an automatic process to get a behavioral and structural description of logic circuits and netlists that are directly technologically feasible. The hardware description language used should be independent of the target technology.
In hardware design, system-on-chip architectures and modeling methods play a key role. The central data processing architecture is based on the the Register-Transfer Level model.

Materialien

File Version Description
pdl2k.script.pdf 06.02.20 Skript
pdl2k0.html 23.10.19 Foliensatz Modul 0
pdl2kA.html 23.10.19 Foliensatz Modul A
pdl2kB.html 23.10.19 Foliensatz Modul B
pdl2kC.html 18.11.19 Foliensatz Modul C
pdl2kD.html 25.11.19 Foliensatz Modul D
pdl2kE.html 02.12.19 Foliensatz Modul E
pdl2kF.html 02.12.19 Foliensatz Modul F
pdl2kG.html 13.01.20 Foliensatz Modul G
pdl2kH.html 06.01.20 Foliensatz Modul H
pdl2kI.html 06.01.20 Foliensatz Modul I
tp.js 4.11.19 Beispiel SigFlow Modell Tiefpassfilter

Aufgaben

File Version Description
tutorial2.html 2.12.19 Interaktives BA und BDD Tutorial mit Übung
workbook-pdl2k-1.json 13.01.20 Workbook Template für VHDL Übung 1
workbook-pdl2k-2.json 20.01.20 Workbook Template für VHDL Übung 2

Software

File Version Description
sigflow.html 1.2.3 Digital Signal Flow Simulator (requires Browser)
bool.html 23.10.19 Boolean Solver (requires Browser)
Retro_V4.3.jar 4.3 Register Transfer Logic Simulator (requires Java). Execute: java -jar Retro_V4.3.jar
RetroUserManual.PDF 4.3 Register Transfer Logic Simulator (Manual)
blocklyvhdl.html Demo BlocklyVHDL - Visual programming editor for VHDL (requires Browser)
workbook.html 1.1.21 Interaktives Workbook (Browser)
winxp-xil.vdi 050419 VirtualBox WINXP + Xilinx11 (small environment) Image (requires VirtualBox 5 and Extension Pack)
xusb_driver.zip 050419 XIlinx USB Cable Driver (Windows)
VirtualBox-5.2.6.exe 5.2.6 VirtualBox Windows X86
VirtualBox-5.2.6-Extensions.extpack 5.2.6 VirtualBox Extension Pack Windows X86
npp-7.5.4.exe 7.5.4 NotePad+ Windows Text Editor
mimasConfig.exe 2019 Numato Lab Mimas FPGA Board Konfiguration (Windows)
MimasConfigPython.zip 2019 Numato Lab Mimas FPGA Board Konfiguration Paket (Linux)
mimasconfig 2019 Numato Lab Mimas FPGA Board Konfiguration Tool+ (Linux)
APK 1.30 Android APK Serial Bluetooth Terminal App.

Inhalte

  1. Motivation and introduction

    • Use and limitations of classical microprocessors in digital signal processing
    • Digital signal processing and applications
    • Data and control flow in digital signal processing
    • Sequential systems and parallelism
    • Benefits of custom parallel systems
    • Configurable processors as an alternative
    • State machines and register transfer logic

  2. Introduction to Fundamentals of Digital Logic and Boolean Algebra

    • Basic logic functions and technical implementation
    • Transistor logic
    • Boolean algebra, normal forms, and logic minimization
    • KV diagrams and procedures according to Quine and McCluskey
    • Combinatorial Logic - Arithmetic Functions

  3. "Programmable" logic devices: MUX, RAM/ROM, GAL, PAL, CPLD, FPGA, ASIC

  4. Simple digital systems with combinatorial logic

  5. Register-transfer based sequential systems

  6. State machines: their application and realization

  7. Introduction to VHDL (in parallel to the above content)

    • Interface Description
    • Architecture
    • Configuration
    • Data objects, control elements

  8. Basics of Digital Logic Synthesis and Synthesis Techniques

  9. Levels in Digital Electronics Design
    • System level
    • Algorithmic level
    • Register transfer level
    • Logic level
    • Electronic circuits